Packages for power semiconductor wafers must operate in a variety of different environments and must meet many different requirements. Such packages must provide a housing for the wafer which is secure from external environmental influences which might otherwise damage the wafer. They must provide for electrical connections to the wafer in a manner which is convenient and does not compromise the protection from the environment. They must provide a cool thermal environment for the wafer and must contact the wafer with materials which permit the wafer to expand and contract with changes in temperature, without causing excessive stresses in the wafer or supportive material. Such packages are also desirably light in weight, compact in size, and easily fabricated using known technologies.
Prior art packages for power semiconductor wafers typically comprise some combination of metals, plastics and ceramics, each of which compromises one aspect of functionality to emphasize another. For example, high thermal conductivity metals such as copper and aluminum can provide excellent heat removal characteristics, but differ substantially from the silicon wafer in thermal expansion. These metals thus cause thermal fatigue and premature failure at the interfaces between the wafer and package. Some ceramic material may be selected to more closely match the thermal expansion of the wafer, but do not provide for easy electrical connection to the wafer. Some plastic materials may be easily fabricated into various package configurations, but these plastics may not provide for heat removal or electrical connections. In short, while various combinations and types of plastics, metals and ceramics can be used to fabricate packages with selected functional characteristics, each of these materials has its own drawbacks which makes its use in the package to some extent undesirable.
It would be desirable to provide a package for a power semiconductor wafer which provides a hermetic seal from the operating environment, simple electrical connection to the wafer, efficiency of cooling, thermal expansion similar to that of the wafer, low weight and compact size, and which may be fabricated using conventional technology. In the above-noted U.S. Pat. No. 4,745,455, there is disclosed a semiconductor package designed to accomplish the above noted objectives by utilizing substantially entirely silicon materials selected to have coefficients of thermal expansion matching that of the power semiconductor. The package disclosed therein incorporates a silicon glass sidewall which operates to form a hermetic seal for the package by bonding or other attachment to doped silicon layers which serve both as electrical terminals and also as part of an enclosure for the semiconductor.
This invention is directed to an improved method for bonding silicon glass to silicon generally and, in particular, to an improved glass to silicon bonding technique which is useful in the manufacture of the silicon package disclosed in the above-noted patent.
Prior art methods for bonding glass to silicon usually involved laying down a metal layer on the glass by sputtering or other means. The metal can subsequently be bonded to a similar layer on silicon by applying heat and pressure or alternately by soldering. Problems of metallization peeling or solder dewetting commonly arise with such techniques.
Glass has been bonded directly to glass by contacting the members and heating them to about 300.degree. C. in the presence of strong electric fields.